CYW173SXC【PDF 2/5 页】IC CLK GEN TAPE DRV 4CH 16SOIC

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Sheet目录1992

1页 [2页]3页 4页 5页

W173

......... Document #: 38-07313 Rev. *B Page Page 2 of 5 of 5

Note:

1. All inputs, except X1 or X2, have an internal pull-up resistor. Unconnected inputs will assume a logic HIGH condition.

Pin Definitions [1]

Pin Name

Pin No.

Pin Type

Pin Description

Output Enable: When LOW, this input signal puts all outputs into a high-impedance

state.

13.2MHZ

Clock Output: Provides a TTL-level timing signal proportional in frequency to the

input signal. For a 26.5625 MHz reference, the frequency will be 13.2 MHz.

6.6MHZ

Clock Output: Provides a TTL-level timing signal proportional in frequency to the

input signal. For a 26.5625 MHz reference, the frequency will be 6.6 MHz.

10MHZ

Clock Output: Provides a TTL-level timing signal proportional in frequency to the

input signal. For a 26.5625 MHz reference, the frequency will be 10.0 MHz.

50MHZ

Clock Output: Provides a TTL-level timing signal proportional in frequency to the

input signal. For a 26.5625 MHz reference, the frequency will be 50.0 MHz.

External Crystal Connection: This pin has dual functions. It can be used as an

external 26.5625 MHz crystal connection or as an external reference frequency

input.

External Crystal Connection: An input connection for an external 26.5625 MHz

crystal. If using an external reference, this pin must be left unconnected.

VDD

1, 6, 9, 12, 16

Power Supply Connections: Connect both VDD pins to the same voltage, either

3.3V or 5.0V. Each VDD pin should have a decoupling capacitor (such as 0.1 F)

placed as close to the pin as possible.

GND

4, 8, 11, 14

Ground Connections: Connect all ground pins to the common system ground

plane.

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